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NXP Semiconductors /MIMXRT1064 /LPUART1 /PINCFG

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Interpret as PINCFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRGSEL_0)TRGSEL

TRGSEL=TRGSEL_0

Description

LPUART Pin Configuration Register

Fields

TRGSEL

Trigger Select

0 (TRGSEL_0): Input trigger is disabled.

1 (TRGSEL_1): Input trigger is used instead of RXD pin input.

2 (TRGSEL_2): Input trigger is used instead of CTS_B pin input.

3 (TRGSEL_3): Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data